The present invention relates to a data processing apparatus including an SIMD (Single Instruction Multiple Data) processor and a host CPU (Central Processing Unit) for controlling the SIMD processor and, more particularly, to a data processing apparatus capable of efficiently controlling an SIMD processor.
In recent years, with the popularization of a portable terminal device, a digital household electrical appliance, and the like, the importance of a digital signal process for processing a large amount of data such as sound and images at high speed is increasing. One of methods of performing such digital signal process at high speed is a method of making an SIMD processor perform the process. In another method, the digital signal process is performed by using a DSP (Digital Signal Processor).
Generally, as described in Japanese Unexamined Patent Application Publication Nos. 2006-99232, 2006-164183, 2006-127460, and 2008-47031, an SIMD processor is coupled to a bus like a normal peripheral IP (Intellectual Property). In many cases, a host CPU performs another process while controlling the SIMD processor. Japanese Unexamined Patent Application Publication No. H09-22379 discloses a processor having a host CPU that controls a DSP.